Thursday, May 28, 2020

Thesis on Time to Digital Converter for SPADs

Universitat Politecnica Valencia, Spain, publishes MSc Thesis "Time to Digital and Charge to Digital converters for SiPM front ends" by Alessandro Morini.

"Two tasks have been carried out in this master thesis: implementation of a single front-end channel (composed by an amplifier and a gated integrator) taking into account specification have been set in advance; a survey on a Time to Digital Converter (TDC) and Analog to Digital Converter (ADC).

The first one accomplishes firstly a preamplifier for the integrated SiPM using a 0.35 um technology. The output current will feed a TDC (boosted for fast signals) and an ADC (boosted for charge integration). During the second step a gated charge integrator has been carried out, which will be used for the analog chain needed for the ADC. It has been settled an integration start threshold and a configurable integrating window.

Regarding the second task, we focused on different configurations for TDC that could work with the given requirements. Furthermore, a Sample and Hold (S/H) and a Successive Approximation ADC (SAR) have been implemented. The SAR is composed by a quite fast comparator, a programmed logic in Verilog-A, necessary to study bit by bit, and a DAC in the end.

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