Tuesday, January 14, 2020

SPAD PDP Simulation

National Chiao Tung University, Taiwan paper "Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes" by Chin-An Hsieh, Chia-Ming Tsai, Bing-Yue Tsui, Bo-Jen Hsiao, and Sheng-Di Lin is a part of MPDI Special issue on the 2019 International Image Sensor Workshop (IISW2019).

"Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication."

1 comment:

  1. Very interesting results. The QE curves definitely show significant problems with surface passivation. The modeling should be extended to incorporate top surface recombination and recombination lifetime in the P-type region of the device (S and tau are not independent) in order to match the quantum efficiency curves using TCAD. A complete model would then use TCAD modeling to estimate the thermal generation rate, which might enable an independent determination of tau. Even 1D modeling in the center of the device would provide significant insight.

    I would like to see this approach applied to other CMOS devices to determine the validity of the fit.

    I would like to see this methodology applied to other CMOS processes to see if the results are universal.


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