Tuesday, August 25, 2020

TSMC Updates on CIS Process Development

AnandTech: TSMC Technology Symposium being held on-line these days shows the foundry's lineup of the processes. The most advanced CIS process in development is 28nm, while the logic process is 7 generations ahead at 3nm:


TodayUSStock posts few more slides form the Symposium:

Posted by Vladimir Koifman at 19:12

6 comments:

  1. CircuitsAugust 25, 2020 at 9:03 PM

    what is maximum CIS Mega pixels in 2020 available in market?

    ReplyDelete
  2. AnonymousAugust 25, 2020 at 11:04 PM

    Sony and Samsung use 65 nm design rule for main process.
    How come TSMC use 28 nm?
    To compensate performance gap with advanced rule?

    ReplyDelete
    Replies
    1. Eric R FossumAugust 26, 2020 at 5:49 PM

      What performance gap? TSMC does not sell its own sensors so for sure there is a marketing gap.

      Delete
    2. AnonymousAugust 26, 2020 at 11:17 PM

      Well... Photodiode process is independent of transistor design rule.
      Their photodiode process capability is poor, then suffer from poor FWC.
      Addressing this issue is that TSMC uses advanced node to enhance a fill factor.
      Other performance such as dark current, white blemish, RTS noise are inferior as well.

      Delete
  3. AnonymousAugust 26, 2020 at 7:52 AM

    as far as I know its Canon 2U250MRXS (https://canon-cmos-sensors.com/canon-2u250mrxs-250mp-cmos-sensor/) 19568x12588 = 246.3MP

    ReplyDelete

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