Tuesday, August 25, 2020

TSMC Updates on CIS Process Development

AnandTech: TSMC Technology Symposium being held on-line these days shows the foundry's lineup of the processes. The most advanced CIS process in development is 28nm, while the logic process is 7 generations ahead at 3nm:

TodayUSStock posts few more slides form the Symposium:


  1. what is maximum CIS Mega pixels in 2020 available in market?

  2. Sony and Samsung use 65 nm design rule for main process.
    How come TSMC use 28 nm?
    To compensate performance gap with advanced rule?

    1. What performance gap? TSMC does not sell its own sensors so for sure there is a marketing gap.

    2. Well... Photodiode process is independent of transistor design rule.
      Their photodiode process capability is poor, then suffer from poor FWC.
      Addressing this issue is that TSMC uses advanced node to enhance a fill factor.
      Other performance such as dark current, white blemish, RTS noise are inferior as well.

  3. as far as I know its Canon 2U250MRXS (https://canon-cmos-sensors.com/canon-2u250mrxs-250mp-cmos-sensor/) 19568x12588 = 246.3MP


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