Monday, April 06, 2020

Analog-to-Information CMOS Sensor for Image Recognition

CEA-Leti publishes a PhD Thesis "Exploring analog-to-information CMOS image sensor design taking advantage on recent advances of compressive sensing for low-power image classification" by Wissam Benjilali.

"Recent advances in the field of CMOS Image Sensors (CIS) tend to revisit the canonical image acquisition and processing pipeline to enable on-chip advanced image processing applications such as decision making. Despite the tremendous achievements made possible thanks to technology node scaling and 3D integration, designing a CIS architecture with on-chip decision making capabilities still a challenging task due to the amount of data to sense and process, as well as the hardware cost to implement state-of-the-art decision making algorithms.

In this context, Compressive Sensing (CS) has emerged as an alternative signal acquisition approach to sense the data in a compressed representation. When based on randomly generated sensing models, CS enables drastic hardware saving through the reduction of Analog to Digital conversions and data off-chip throughput while providing a meaningful information for either signal recovery or signal processing. Traditionally, CS has been exploited in CIS applications for compression tasks coupled with a remote signal recovery algorithm involving high algorithmic complexity. To alleviate this complexity, signal processing on CS provides solid theoretical guarantees to perform signal processing directly on CS measurements without significant performance loss opening as a consequence new ways towards the design of low-power smart sensor nodes.Built on algorithm and hardware research axes, this thesis illustrates how Compressive Sensing can be exploited to design low-power sensor nodes with efficient on-chip decision making algorithms.

After an overview of the fields of Compressive Sensing and Machine Learning with a particular focus on hardware implementations, this thesis presents four main contributions to study efficient sensing schemes and decision making approaches for the design of compact CMOS Image Sensor architectures. First, an analytical study explores the interest of solving basic inference tasks on CS measurements for highly constrained hardware. It aims at finding the most beneficial setting to perform decision making on Compressive Sensing based measurements.

Next, a novel sensing scheme for CIS applications is presented. Designed to meet both theoretical and hardware requirements, the proposed sensing model is shown to be suitable for CIS applications addressing both image rendering and on-chip decision making tasks. On the other hand, to deal with on-chip computational complexity involved by standard decision making algorithms, new methods to construct a hierarchical inference tree are explored to reduce MAC operations related to an on-chip multi-class inference task. This leads to a joint acquisition-processing optimization when combining hierarchical inference with Compressive Sensing.

Finally, all the aforementioned contributions are brought together to propose a compact CMOS Image Sensor architecture enabling on-chip object recognition facilitated by the proposed CS sensing scheme, reducing as a consequence on-chip memory needs. The only additional hardware compared to a standard CIS architecture using first order incremental Sigma-Delta Analog to Digital Converter (ADC) are a pseudo-random data mixing circuit, an +/-1 in-Sigma-Delta modulator and a small Digital Signal Processor (DSP). Several hardware optimization are presented to fit requirements of future ultra-low power (≈µW) CIS design.


  1. This random shuffling has been published long time ago.

    1. Albert Theuwissen - Harvest ImagingApril 6, 2020 at 9:39 PM

      You are right, this was published by Martijn Snoeij at ISSCC 2006 and JSSC 2006. Unfortunately these publications are not referenced in the thesis ... Too bad.

  2. Dear Dr. Theuwissen,
    Thank you for the reference (not easy to identify in the large context covered by the thesis in the absence of clear key-words). However, I'd like to emphasize the fact that the fully connected or block-based pseudo-random multiplexers are just examples of implementation used to introduce/discuss the final implementation (i.e., Benes network-based permutations) which is shown to be more hardware friendly in terms of silicon area.
    Best regards,


All comments are moderated to avoid spam and personal attacks.