Saturday, April 25, 2020

EPFL Proposes 5T Pixel with 0.32e- Noise and Enhanced DR

IEEE Electron Device Letters gives an early access to EPFL paper "A CMOS Image Sensor Pixel Combining Deep Sub-electron Noise with Wide Dynamic Range" by Assim Boukhayma, Antonino Caizzone, and Christian Enz.

"This letter introduces a 5-transistors (5T) implementation of CMOS Image Sensors (CIS) pixels enabling the combination of deep sub-electron noise performance with wide dynamic range (DR). The 5T pixel presents a new technique to reduce the sense node capacitance without any process refinements or voltage level increase and features adjustable conversion gain (CG) to enable wide dynamic imaging. The implementation of the proposed 5T pixel in a standard 180 nm CIS process demonstrates the combination of a measured high CG of 250 μV/e- and low CG of 115 μV/e- with a saturation level of about 6500 e- offering photo-electron counting capability without compromising the DR and readout speed."

"Thanks to the high CG of 250 µV/e− and optimized PMOS SF, the read noise is as low as 0.32 e− RMS. This result is confirmed by Fig. 5 obtained by plotting the histogram of 1500 pixel outputs while the chip is exposed to very low input light. The histogram features peaks and valleys where each peak corresponds to a charge quantum."

"The reset phase consists in three steps. First, the RST switch is closed connecting IN to VRST. While VRST is set to VDD, the potential barrier between IN and SN is lowered by setting TX2 to a voltage VTX2H1 in order to dump the charge from the SN as depicted in Fig. 2(a). TX2 is set back to 0 in order to split the IN and SN and freeze the SN voltage at its maximum level.

VRST is then switched to a lower voltage VRSTL between the pin voltage of the PPD Vpin and VSN,max. After this step, the reset switch is opened again to freeze the IN voltage at a value VIN as depicted in Fig. 2(b). The last step of the reset phase consists in setting TX2 to a voltage VTX2H2 making the barrier between the IN and SN equal or slightly higher than VIN as shown in Fig. 2(c). In this way, any excess charge transferred to IN would diffuse towards the SN.

After lowering back TX2, the SN reset voltage VSN,rst is sensed. Transferring the charge integrated in the PPD to the SN takes place by pulsing both TX1 and TX2 as depicted in Fig. 2(d). TX1 is pulsed to a value VTX1H in order to set the voltage under the TG between the PPD pin voltage Vpin and the intermediate node voltage VIN while TX2 is pulsed again to transfer this charge to the SN. The signal corresponds to the difference between the SN
voltage after reset VSN,rst and the one sensed after the transfer VSN,transfer.

Update: The paper is also published in IEEE EDL.


  1. It seems it's not a SF architecture. It's a common-source with source degeneration as negative feedback to reduce the gain variation and give better input common mode range. This structure has lots of issues when use it in an array of pixels. Gain variation, linearity issues, swing issues. Maybe that's why they did not present any output image in this paper. Similar to some of Albert's recent works.

  2. I wonder how the charge transfer between IN and SN can be lag-free?

  3. The paper has several technological issues, but it also has a few interesting ideas. It is good to publish these papers to give us new ideas and of course, the chance to improve their implementation so as to solve the afore-mentioned issues.

    The lag of 10% is pretty substantial, but even the baseline 4T device seems to have substantial lag. Lag from IN will depend on its capacitance, and perhaps for some applications, the lag is not critical. For true photon-counting applications, the lag is critical and I am not convinced a single photoelectron won't get lost or delayed in IN depending on the history. Nevertheless, it is important to me that new ideas, even if not perfect, get published and shared.

    1. Also, some concern about the PCH peaks not being regularly spaced, or so it seems, and concern about the negative photoelectron-number "peaks." Probably more measurements of the PCH would lead to a clearer result. And if it didn't, that would also be a source of concern.

  4. No physics under the device operation is given, this is not a good paper.

  5. I guess different kTC noise level between IN and SN node would prevent charge transfer from IN to SN.

  6. My feeling is that body-effect less PMOS source follower does remove the gate capacitance by Miller effect. So the only capacitance on SN node will be the tiny diffusion and some stray capacitance, their value is small and the consequent conversion gain is high.
    So it's possible to have single electron detection on SN node. Then photo electrons generated by PPD will be able to reach SN node with non-unity probability. If the image lag is ignored, then it impacts the equivalent QE by some kind of 'excess noise factor' ...


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