Hynix on Key CIS Technologies

 SK Hynix publishes an article "Applying Light to Semiconductors: Introducing to CIS Key Process Technologies."

"The pixel size should be more reduced to increase the number of pixels in the same chip size. Also, forming deep PD is a key technology to avoid deterioration in image quality. To secure sufficient full well capacity (FWC) in small pixels, patterning and implementing technologies with higher difficulty level compared to the ones for semiconductor memory are required. Especially, it is essential to secure a high aspect ratio (>15:1) implant MASK process technology that can block high-energy ion implantation; in fact, the aspect ratio tends to be gradually increasing in the industry these days.

The technology to isolate pixels from one another is very important to make a high-definition CIS. A less developed isolation technology can cause various image defects such as color mixing and color spreading. Each chipmaker has different isolation technology, and the difference will be an important criterion for image quality in the CIS market where higher pixel density and higher resolution are becoming common standards. Various issues can occur during the isolation process. For this reason, huge efforts are being made to select better equipment and develop new recipes to improve yield and product quality.

One of the most fundamental requirements in the CIS product development and mass production process is to control metallic contamination. Since CIS products are sensitive to contamination several times more than memory products and the contamination directly affects product yield and quality, various contamination control technologies are required. The next important factor is the plasma damage control. Since the deterioration of image properties such as hot pixels occurs due to the damage caused during the process, it is necessary to manage key processes accurately."