Monday, July 12, 2021

Sony's View on Stacked CIS Evolution

IEICE ESS Fundamentals Review publishes Sony paper "Evolving Image Sensor Architecture through Stacking Devices" by Yusuke OIKE. Unfortunately, there is no English version available and the pdf is protected from copying the text for an on-line translation.

"The evolution of CMOS image sensors and the prospects utilizing advanced imaging technologies promise to improve our quality of life. CMOS image sensors now dominate the market of digital cameras with the advent of parallel ADCs and back-illuminated technology. Moreover stacked CMOS image sensors continue to enhance functionality and user experience in mobile devices. We introduce the evolution of image sensor architecture for accelerating drastic performance improvements and for integrating edge computing connected to the sensor layer through stacking technologies. Furthermore, the fine pitch connection between the pixel and logic layers makes pixel parallel circuit architecture practical for the next stage of evolution."

7 comments:

  1. The images look similar to the talk given by Oike-san during the 3DIC forum at this years ISSCC- I suspect the content is the same (in case people are curious and have access to that material)

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  2. It seems also Sony is pushing for die to wafer or die to die bonding in the future. We will see a boom in this technology soon I think. It still seems to be hard to do, the required precision and clenliness for example, but the machines will evolve quite quickly as the sonys, intels, tsmcs etc. of this world seem to pour a lot of money on it...

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  3. I have the English version of this paper if you're interested.

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  4. Can you please share the English version of the paper with me? I'm interested in it. Thanks.

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    Replies
    1. Sure. How do I send it to you?

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    2. Can you please send it to my email address rzhou2015@gmail.com
      Thanks a million.

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    3. If it's open access paper, please send it to me and I'll publish it

      Delete

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