Monday, October 01, 2018

IEDM 2018 Image Sensor Papers

IEDM 2018 to be held on Dec. 1-5 in San Francisco publishes a list of accepted papers with an interesting image sensor stuff:
  • High Performance 2.5um Global Shutter Pixel with New Designed Light-Pipe Structure
    Toshifumi Yokoyama, TowerJazz Panasonic Semiconductor Co.
  • Back-Illuminated 2.74 μm-Pixel-Pitch Global Shutter CMOS Image Sensor with Charge-Domain Memory Achieving 10k e- Saturation Signal
    Yoshimichi Kumagai, Sony Semiconductor
  • A 0.68e-rms Random-Noise 121dB Dynamic-Range Sub-pixel architecture CMOS Image Sensor with LED Flicker Mitigation
    Satoko Iida, Sony Semiconductor
  • A 24.3Me- Full Well Capacity CMOS Image Sensor with Lateral Overflow Integration Trench Capacitor for High Precision Near Infrared Absorption Imaging
    Maasa Murata, Tohoku University
  • A HDR 98dB 3.2µm Charge Domain Global Shutter CMOS Image Sensor
    Arnaud Tournier, STMicroelectronics
  • 1.5µm dual conversion gain, backside illuminated image sensor using stacked pixel level connections with 13ke- full-well capacitance and 0.8e- noise
    Vincent Venezia, Omnivision
  • Through-silicon-trench in back-side-illuminated CMOS image sensors for the improvement of gate oxide long term performance
    Andrea Vici, La Sapienza University of Rome
  • High-Performance Germanium-on-Silicon Lock-in Pixels for Indirect Time-of-Flight Applications
    Neil Na, Artilux Inc.
  • High Voltage Generation Using Deep Trench Isolated Photodiodes in a Back Side Illuminated Process
    Filip Kaklin, The University of Edinburgh
  • CMOS-Integrated Single-Photon-Counting X-Ray Detector using an Amorphous-Selenium Photoconductor with 11×11-μm2 Pixels
    Ahmet Camlica, University of Waterloo

1 comment:

  1. There's also this one, which unfortunately overlaps with the imager session papers:

    7.3 Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness, J. Jourdon, et al, STMicroelectronics, *University of Bordeaux, **CEA-LETI

    abstracts are published meanwhile too: for the above one: "We present the first 3D-stacked CMOS Image Sensor with a bonding pitch of 1.44 µm. The influence of the hybrid bonding pitch shrinkage (8.8 to 1.44 μm) from the process point of view to a functional device via the robustness aspect is studied. Smaller bonding pads do not lead to any specific failure "


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