Wednesday, February 25, 2015

ISSCC 2015 Report

Albert Theuwissen starts publishing his overview of ISSCC 2015 imaging session. The first part talks about the new Sony 20MP/1.43um stacked sensor with two ADCs per column. The dual ADC can be used:
  • for increased readout speed (120fps in 16MP/10b mode)
  • for 3db noise improvement
  • to achieve 1.3e- noise level by multiple reads
  • simultaneous stills and video capture


  1. In the talk Sony mentions that the die size of the stacked image sensor is reduced, and the imaging area is increased. They said the imaging area was increased to 1/1.7-inch format (1.43 um pixel) since this was a DSC application and not for mobile. But unfortunately no one asked about the total die cost since now two die are required per sensor instead of the baseline one die.
    Noise reduction of -3 dB is achieved by their sampling scheme at an extra cost of 116mW. I also wished someone had asked about other ways one might spend 116mW to reduce noise (e.g. bias current). Anyway, there seemed to a few papers talking about reconfiguring chips on the fly for different modes including this Sony paper. I was not impressed with this particular sort of cleverness using a lot of switches, but I suppose it has its uses.

    Lastly, aside from the European SPAD work in the life sciences imaging session, the image sensors papers were all from Asia. (The NHK-Japan paper was co-authored by Forza-USA). This is really too bad but fortunately does not reflect the diversity we see in the 150+ abstracts submitted to 2015 IISW.

  2. Do they use always single-slope column ADC?

  3. I guess that the SS-ADC counts at xGhz, so 116mW consumption is really a miracle!


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