Looks there's an error on slide 7? The gate of the load of the left part of the differential pair is only connected to another node. The terminal is always high-impedance. I presume this was supposed to be a MOS-diode?
Yes, there is a mistake. A connection dot is missing that between this high-impedance node and a drain of the right side pfet in the diff pair. The two nfets under the diff pair are supposed to form a cross-coupled latch that is reset by CK signal.
Looks there's an error on slide 7? The gate of the load of the left part of the differential pair is only connected to another node. The terminal is always high-impedance. I presume this was supposed to be a MOS-diode?
ReplyDeleteYes, there is a mistake. A connection dot is missing that between this high-impedance node and a drain of the right side pfet in the diff pair. The two nfets under the diff pair are supposed to form a cross-coupled latch that is reset by CK signal.
DeleteI see - thank you!
Delete